mirror of https://github.com/zachjs/sv2v.git
10 lines
171 B
Systemverilog
10 lines
171 B
Systemverilog
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// pattern: illegal mix of ordered and named port connections
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module example(
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input a, b, c
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);
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endmodule
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module top;
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wire a, b, c;
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example e(1, .*);
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endmodule
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