forbid mixing ordered and named port or param bindings

src/Language/SystemVerilog/Parser/Parse.y

@@ -966,7 +966,7 @@ LHSs :: { [LHS] }
 
 PortBindings :: { [PortBinding] }
   : "("                    ")" { [] }
-  | "(" PortBindingsInside ")" { $2 }
+  | "(" PortBindingsInside ")" {% checkPortBindings $2 }
 PortBindingsInside :: { [PortBinding] }
   : PortBinding opt(",")               { [$1] }
   | PortBinding "," PortBindingsInside { $1 : $3}
@@ -978,7 +978,7 @@ PortBinding :: { PortBinding }
 
 ParamBindings :: { [ParamBinding] }
   : "#" "("                     ")" { [] }
-  | "#" "(" ParamBindingsInside ")" { $3 }
+  | "#" "(" ParamBindingsInside ")" {% checkParamBindings $3 }
 ParamBindingsInside :: { [ParamBinding] }
   : ParamBinding opt(",")                { [$1] }
   | ParamBinding "," ParamBindingsInside { $1 : $3}
@@ -1506,4 +1506,19 @@ missingToken expected = do
   p <- gets pPosition
   throwError $ show p ++ ": Parse error: missing expected `" ++ expected ++ "`"
 
+checkPortBindings :: [PortBinding] -> ParseState [PortBinding]
+checkPortBindings = checkBindings "port connections"
+
+checkParamBindings :: [ParamBinding] -> ParseState [ParamBinding]
+checkParamBindings = checkBindings "parameter overrides"
+
+checkBindings :: String -> [(Identifier, a)] -> ParseState [(Identifier, a)]
+checkBindings kind bindings =
+  if all null bindingNames || all (not . null) bindingNames then
+    return bindings
+  else do
+    p <- gets pPosition
+    error $ show p ++ ": Parse error: illegal mix of ordered and named " ++ kind
+  where bindingNames = map fst bindings
+
 }

test/error/binding_mix_param.sv

@@ -0,0 +1,11 @@
+// pattern: illegal mix of ordered and named parameter overrides
+module example #(
+    parameter P = 1, Q = 2
+) (
+    input a, b, c
+);
+endmodule
+module top;
+    wire a, b, c;
+    example #(1, .Q(2)) e(.*);
+endmodule

test/error/binding_mix_port.sv

@@ -0,0 +1,9 @@
+// pattern: illegal mix of ordered and named port connections
+module example(
+    input a, b, c
+);
+endmodule
+module top;
+    wire a, b, c;
+    example e(1, .*);
+endmodule