mirror of https://github.com/zachjs/sv2v.git
8 lines
158 B
Verilog
8 lines
158 B
Verilog
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module top;
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`define TEST(subroutine) \
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initial repeat (4) $display(`"subroutine()`");
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`TEST(dump)
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`TEST(P::dump)
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`TEST(C#(1)::dump)
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endmodule
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