mirror of https://github.com/zachjs/sv2v.git
6 lines
116 B
Verilog
6 lines
116 B
Verilog
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module top;
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parameter W = 8;
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reg [W - 1:0] x = 8'b1101_0100;
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wire [W - 1:0] y = 8'b0010_1011;
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endmodule
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