mirror of https://github.com/zachjs/sv2v.git
7 lines
147 B
Verilog
7 lines
147 B
Verilog
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module top;
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localparam L0 = 0;
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localparam L1 = L0;
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localparam L2 = $clog2(L1);
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initial $display("%b %b %b", L0, L1, L2);
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endmodule
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