mirror of https://github.com/zachjs/sv2v.git
6 lines
86 B
Verilog
6 lines
86 B
Verilog
|
module top;
|
||
|
|
Example e1();
|
||
|
|
Example #(8) e2();
|
||
|
|
Example #(9) e3();
|
||
|
|
endmodule
|