mirror of https://github.com/zachjs/sv2v.git
7 lines
155 B
Verilog
7 lines
155 B
Verilog
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module top;
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localparam W = 4;
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localparam A = 4'b1010;
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localparam B = 4'b0101;
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initial $display("%d %d %d %b %b", W, W, W, A, B);
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endmodule
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