mirror of https://github.com/zachjs/sv2v.git
26 lines
490 B
Verilog
26 lines
490 B
Verilog
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module top;
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genvar i;
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generate
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initial #1;
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`define PRINT(X, offset) \
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for (i = 4; i <= 8; i = i + 1) \
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initial begin \
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$display(`"Module``X got %0d`", i ** 2 + offset); \
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$display("ModuleN got %0d", i ** 2 + offset); \
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end
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`PRINT(A, 0)
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`PRINT(A, 1)
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`PRINT(A, 2)
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`PRINT(B, 1)
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`PRINT(B, 1)
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`PRINT(C, 2)
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`PRINT(C, 2)
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endgenerate
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endmodule
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