mirror of https://github.com/zachjs/sv2v.git
11 lines
230 B
Systemverilog
11 lines
230 B
Systemverilog
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interface Interface;
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logic x;
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endinterface
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module top;
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Interface intfs[3:2][8:5]();
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for (genvar x = 2; x <= 3; x = x + 1)
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for (genvar y = 5; y <= 8; y = y + 1)
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assign intfs[x][y].x = '1;
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endmodule
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