mirror of https://github.com/zachjs/sv2v.git
12 lines
209 B
Verilog
12 lines
209 B
Verilog
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module top;
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reg signed [31:0] inp;
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wire signed [31:0] out;
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Example e(inp, out);
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initial begin
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#1 inp = 1;
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#1 inp = 5;
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#1 inp = 10;
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#1 inp = 7;
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end
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endmodule
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