don't force int types to be regs

src/Language/SystemVerilog/AST/Type.hs

@@ -144,7 +144,7 @@ elaborateIntegerAtom other = other
 -- size; if not unspecified, the first signing overrides the second
 baseIntType :: Signing -> Signing -> Int -> Type
 baseIntType sgOverride sgBase size =
-    IntegerVector TReg sg [(RawNum hi, RawNum 0)]
+    IntegerVector TLogic sg [(RawNum hi, RawNum 0)]
     where
         hi = fromIntegral $ size - 1
         sg = if sgOverride /= Unspecified

test/basic/input_int.sv

@@ -0,0 +1,6 @@
+module Example(
+    input int inp,
+    output int out
+);
+    assign out = inp * 2;
+endmodule

test/basic/input_int.v

@@ -0,0 +1,6 @@
+module Example(
+    input wire signed [31:0] inp,
+    output wire signed [31:0] out
+);
+    assign out = inp * 2;
+endmodule

test/basic/input_int_tb.v

@@ -0,0 +1,11 @@
+module top;
+    reg signed [31:0] inp;
+    wire signed [31:0] out;
+    Example e(inp, out);
+    initial begin
+        #1 inp = 1;
+        #1 inp = 5;
+        #1 inp = 10;
+        #1 inp = 7;
+    end
+endmodule

test/basic/interface_based_typedef.sv

@@ -7,8 +7,12 @@ module sub(intf_i p, intf_i q [2]);
     typedef q[0].data_t q_data_t; // interface based typedef
     p_data_t p_data;
     q_data_t q_data;
-    initial $display("p %0d %b", $bits(p_data), p_data);
-    initial $display("q %0d %b", $bits(q_data), q_data);
+    initial begin
+        p_data = 1;
+        q_data = 2;
+        $display("p %0d %b", $bits(p_data), p_data);
+        $display("q %0d %b", $bits(q_data), q_data);
+    end
 endmodule
 
 module top;

test/basic/interface_based_typedef.v

@@ -1,4 +1,4 @@
 module top;
-    initial $display("p %0d %b", 32, 32'bx);
-    initial $display("q %0d %b", 32, 32'bx);
+    initial $display("p %0d %b", 32, 32'd1);
+    initial $display("q %0d %b", 32, 32'd2);
 endmodule

test/basic/typeof_signed.sv

@@ -14,9 +14,12 @@
 `define ASSERT_UNSIGNED(expr) `ASSERT_SIGNEDNESS(expr, unsigned, 0)
 
 `define MAKE_PRIM(typ) \
-    typ typ``_unspecified = 1; \
-    typ unsigned typ``_unsigned = 1; \
-    typ signed typ``_signed = 1; \
+    typ typ``_unspecified; \
+    typ unsigned typ``_unsigned; \
+    typ signed typ``_signed; \
+    initial typ``_unspecified = 1; \
+    initial typ``_unsigned = 1; \
+    initial typ``_signed = 1; \
     `ASSERT_SIGNED(typ``_signed) \
     `ASSERT_UNSIGNED(typ``_unsigned)
 

test/basic/typeof_signed.v

@@ -1,7 +1,7 @@
-`define MAKE_PRIM(typ, base, size) \
-    base [size-1:0] typ``_unspecified = 1; \
-    base [size-1:0] typ``_unsigned = 1; \
-    base signed [size-1:0] typ``_signed = 1;
+`define MAKE_PRIM(typ, size) \
+    reg [size-1:0] typ``_unspecified = 1; \
+    reg [size-1:0] typ``_unsigned = 1; \
+    reg signed [size-1:0] typ``_signed = 1;
 
 module top;
     wire signed x;
@@ -14,17 +14,17 @@ module top;
     assign w = z;
     initial #1 $display("%b %b %b %b", x, y, z, w);
 
-    `MAKE_PRIM(byte, reg, 8)
-    `MAKE_PRIM(shortint, reg, 16)
-    `MAKE_PRIM(int, reg, 32)
+    `MAKE_PRIM(byte, 8)
+    `MAKE_PRIM(shortint, 16)
+    `MAKE_PRIM(int, 32)
     integer integer_unspecified = 1;
     reg [31:0] integer_unsigned = 1;
     integer integer_signed = 1;
-    `MAKE_PRIM(longint, reg, 64)
+    `MAKE_PRIM(longint, 64)
 
-    `MAKE_PRIM(bit, wire, 1)
-    `MAKE_PRIM(reg, reg, 1)
-    `MAKE_PRIM(logic, wire, 1)
+    `MAKE_PRIM(bit, 1)
+    `MAKE_PRIM(reg, 1)
+    `MAKE_PRIM(logic, 1)
 
     reg signed [5:0] arr;
 endmodule