mirror of https://github.com/zachjs/sv2v.git
10 lines
154 B
Verilog
10 lines
154 B
Verilog
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module top;
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parameter WIDTH = 5;
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reg [WIDTH-1:0] x, y;
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if (WIDTH > 0)
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initial
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x = 0;
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initial
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y = 0;
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endmodule
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