mirror of https://github.com/zachjs/sv2v.git
25 lines
583 B
Verilog
25 lines
583 B
Verilog
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`define IDX(a, r, c) a[(r * 3 + c) * 8 +: 8]
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module mod(
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input clk,
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input [7:0] row, col,
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output [47:0] flat
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);
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function automatic [47:0] f;
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input [47:0] inp;
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integer i, j;
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for (i = 0; i < 2; i = i + 1)
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for (j = 0; j < 3; j = j + 1)
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`IDX(f, i, j) = (i + 1) * (j + 1) * `IDX(inp, i, j);
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endfunction
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reg [47:0] arr;
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reg [47:0] res;
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assign flat = res;
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initial arr = 0;
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always @(posedge clk) begin
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`IDX(arr, row, col) = `IDX(arr, row, col) + 1;
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res = f(arr);
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end
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endmodule
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