mirror of https://github.com/zachjs/sv2v.git
9 lines
142 B
Systemverilog
9 lines
142 B
Systemverilog
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interface Interface(input a, output b);
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assign b = a;
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endinterface
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module top;
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logic a, b, c;
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Interface intf(a, b, c);
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endmodule
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