mirror of https://github.com/zachjs/sv2v.git
12 lines
216 B
Systemverilog
12 lines
216 B
Systemverilog
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// pattern: illegal mix of ordered and named parameter overrides
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module example #(
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parameter P = 1, Q = 2
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) (
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input a, b, c
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);
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endmodule
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module top;
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wire a, b, c;
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example #(1, .Q(2)) e(.*);
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endmodule
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