mirror of https://github.com/zachjs/sv2v.git
7 lines
123 B
Systemverilog
7 lines
123 B
Systemverilog
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module top;
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parameter W = 8;
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logic [W - 1:0] x, y;
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assign y = {<<{x}};
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initial x = 8'b1101_0100;
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endmodule
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