mirror of https://github.com/zachjs/sv2v.git
10 lines
306 B
Verilog
10 lines
306 B
Verilog
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module Example(data, p1, p2, out_x, out_y);
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input wire [31:0] data;
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input wire p1, p2;
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output wire [3:0] out_x;
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output wire [3:0] out_y;
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assign out_x = p2 ? data[p1 * 8 + 20 +:4] : data[p1 * 8 + 16 +:4];
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assign out_y = p2 ? data[p1 * 8 + 4 +:4] : data[p1 * 8 + 0 +:4];
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endmodule
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