mirror of https://github.com/zachjs/sv2v.git
12 lines
213 B
Verilog
12 lines
213 B
Verilog
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module top;
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reg data;
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initial #1 $display("Interface %b", data);
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initial #2 $display("Module %b", data);
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initial begin
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data = 0;
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#1;
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data = 1;
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#1;
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end
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endmodule
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