mirror of https://github.com/zachjs/sv2v.git
12 lines
283 B
Verilog
12 lines
283 B
Verilog
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module top;
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generate
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if (1) begin : block
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wire [3:2][8:5] xs;
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genvar x, y;
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for (x = 2; x <= 3; x = x + 1)
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for (y = 5; y <= 8; y = y + 1)
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assign xs[x][y] = 1'b1;
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end
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endgenerate
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endmodule
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