mirror of https://github.com/zachjs/sv2v.git
23 lines
469 B
Verilog
23 lines
469 B
Verilog
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module top;
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reg clk;
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initial begin
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clk = 0;
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forever
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#1 clk = ~clk;
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end
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reg [7:0] row, col;
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wire [47:0] flat;
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mod m(clk, row, col, flat);
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integer i, j;
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initial begin
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$monitor("%3d %0d %0d %b", $time, row, col, flat);
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repeat (10)
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for (row = 0; row < 2; row = row + 1)
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for (col = 0; col < 3; col = col + 1)
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#2;
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$finish;
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end
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endmodule
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