mirror of https://github.com/zachjs/sv2v.git
15 lines
316 B
Systemverilog
15 lines
316 B
Systemverilog
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module top;
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// The below blocks must be named when converted to Verilog-2005 because it
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// contains a data declaration.
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initial begin
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integer i;
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i = 1;
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$display("%08d", i);
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end
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initial begin
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integer i;
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i = 1;
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$display("%08d", i);
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end
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endmodule
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