mirror of https://github.com/zachjs/sv2v.git
5 lines
84 B
Systemverilog
5 lines
84 B
Systemverilog
|
module top;
|
||
|
|
logic x, y, z;
|
||
|
|
assign {<< {x, '{y:y, z:z}}} = 3'b101;
|
||
|
|
endmodule
|