sv2v/src/Convert/Typedef.hs

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{- sv2v
- Author: Zachary Snow <zach@zachjs.com>
-
- Conversion for `typedef`
-
- Aliased types can (probably) appear in all item declarations, including
- modules, blocks, and function parameters.
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-}
module Convert.Typedef (convert) where
import Control.Monad.Writer
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import qualified Data.Map as Map
import Convert.Traverse
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import Language.SystemVerilog.AST
type Types = Map.Map Identifier Type
convert :: AST -> AST
convert descriptions =
filter (not . isTypedef) $ traverseDescriptions (convertDescription types) descriptions
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where
types = execWriter $ collectDescriptionsM getTypedef descriptions
getTypedef :: Description -> Writer Types ()
getTypedef (Typedef a b) = tell $ Map.singleton b a
getTypedef _ = return ()
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isTypedef :: Description -> Bool
isTypedef (Typedef _ _) = True
isTypedef _ = False
convertDescription :: Types -> Description -> Description
convertDescription types description =
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traverseModuleItems (traverseTypes $ resolveType types) description
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resolveType :: Types -> Type -> Type
resolveType _ (Reg rs) = Reg rs
resolveType _ (Wire rs) = Wire rs
resolveType _ (Logic rs) = Logic rs
resolveType _ (Implicit rs) = Implicit rs
resolveType _ (IntegerT ) = IntegerT
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resolveType _ (Enum Nothing vals rs) = Enum Nothing vals rs
resolveType types (Enum (Just t) vals rs) = Enum (Just $ resolveType types t) vals rs
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resolveType types (Struct p items rs) = Struct p items' rs
where
items' = map resolveItem items
resolveItem (t, x) = (resolveType types t, x)
resolveType types (Alias st rs1) =
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case resolveType types $ types Map.! st of
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(Reg rs2) -> Reg $ rs2 ++ rs1
(Wire rs2) -> Wire $ rs2 ++ rs1
(Logic rs2) -> Logic $ rs2 ++ rs1
(Enum t v rs2) -> Enum t v $ rs2 ++ rs1
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(Struct p l rs2) -> Struct p l $ rs2 ++ rs1
(Implicit rs2) -> Implicit $ rs2 ++ rs1
(IntegerT ) -> error $ "resolveType encountered packed `integer` on " ++ st
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(Alias _ _) -> error $ "resolveType invariant failed on " ++ st