mirror of https://github.com/zachjs/sv2v.git
21 lines
351 B
Verilog
21 lines
351 B
Verilog
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module top;
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reg x, y;
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wire z;
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task t;
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x = 1;
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endtask
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function f;
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input x;
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begin
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y = 1;
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f = 0;
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end
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endfunction
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assign z = 0;
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initial begin
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t;
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$display("%b %b %b %b", x, y, z, f(0));
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$display("%b %b %b %b", x, y, z, f(0));
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end
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endmodule
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