mirror of https://github.com/zachjs/sv2v.git
19 lines
294 B
Verilog
19 lines
294 B
Verilog
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module top;
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task foo;
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integer x;
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begin
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x = 2;
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$display(x * x);
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end
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endtask
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task bar;
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integer y;
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begin
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y = 3;
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$display(y * y);
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end
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endtask
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initial foo;
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initial bar;
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endmodule
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