2019-03-06 20:36:16 +01:00
|
|
|
{- sv2v
|
|
|
|
|
- Author: Zachary Snow <zach@zachjs.com>
|
|
|
|
|
-
|
2019-03-08 02:03:35 +01:00
|
|
|
- Conversion which makes function `logic` and `reg` return types implicit
|
2019-03-06 20:36:16 +01:00
|
|
|
-}
|
|
|
|
|
|
|
|
|
|
module Convert.FuncRet (convert) where
|
|
|
|
|
|
|
|
|
|
import Convert.Traverse
|
|
|
|
|
import Language.SystemVerilog.AST
|
|
|
|
|
|
|
|
|
|
convert :: AST -> AST
|
|
|
|
|
convert = traverseDescriptions $ traverseModuleItems convertFunction
|
|
|
|
|
|
|
|
|
|
convertFunction :: ModuleItem -> ModuleItem
|
2019-03-08 17:02:40 +01:00
|
|
|
convertFunction (MIPackageItem (Function ml t f decls stmts)) =
|
|
|
|
|
MIPackageItem $ Function ml t' f decls stmts
|
|
|
|
|
where
|
|
|
|
|
t' = case t of
|
2019-03-22 21:57:13 +01:00
|
|
|
IntegerVector TReg sg rs -> Implicit sg rs
|
|
|
|
|
IntegerVector TLogic sg rs -> Implicit sg rs
|
2019-03-08 17:02:40 +01:00
|
|
|
_ -> t
|
2019-03-06 20:36:16 +01:00
|
|
|
convertFunction other = other
|