mirror of https://github.com/zachjs/sv2v.git
13 lines
228 B
Verilog
13 lines
228 B
Verilog
|
module top;
|
||
|
|
initial begin : block_name1
|
||
|
|
integer i;
|
||
|
|
i = 1;
|
||
|
|
$display("%08d", i);
|
||
|
|
end
|
||
|
|
initial begin : block_name2
|
||
|
|
integer i;
|
||
|
|
i = 1;
|
||
|
|
$display("%08d", i);
|
||
|
|
end
|
||
|
|
endmodule
|