mirror of https://github.com/zachjs/sv2v.git
6 lines
146 B
Verilog
6 lines
146 B
Verilog
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module top;
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integer w = 11;
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wire [63:0] x = { 32'd11, 32'd12 };
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initial $display("%b %b %b %b", w, x, x[32+:32], x[0+:32]);
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endmodule
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