mirror of https://github.com/zachjs/sv2v.git
21 lines
398 B
Systemverilog
21 lines
398 B
Systemverilog
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module top;
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task t(inout [7:0] x, y);
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begin
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x = ~x;
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if (y) begin
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x = x * 3;
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y = y + 1;
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end
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end
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endtask
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reg [7:0] a, b;
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always @* t(a, b);
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initial begin
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a = 0;
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b = 1;
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$monitor("%d %b %b", $time, a, b);
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repeat (100)
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#5 b = b * 3 - 1;
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end
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endmodule
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