allow inout task and function ports

CHANGELOG.md

@@ -5,6 +5,10 @@
 * Removed deprecated CLI flags `-d`/`-e`/`-i`, which have been aliased to
   `-D`/`-E`/`-I` with a warning since late 2019
 
+### Bug Fixes
+
+* Fixed an issue that prevented parsing tasks and functions with `inout` ports
+
 ## v0.0.11
 
 ### New Features

src/Language/SystemVerilog/Parser/Parse.y

@@ -1604,9 +1604,8 @@ combineDeclsAndStmts (a1, b1) (a2, b2) =
     else return (a1 ++ a2, b1 ++ b2)
 
 makeInput :: Decl -> Decl
-makeInput (Variable Local t x a e) = Variable Input t x a e
-makeInput (Variable Input t x a e) = Variable Input t x a e
-makeInput (Variable Output t x a e) = Variable Output t x a e
+makeInput (Variable d t x a e) = Variable d' t x a e
+  where d' = if d == Local then Input else d
 makeInput (CommentDecl c) = CommentDecl c
 makeInput other =
   error $ "unexpected non-var or non-port function decl: " ++ (show other)

test/basic/task_inout.sv

@@ -0,0 +1,20 @@
+module top;
+    task t(inout [7:0] x, y);
+        begin
+            x = ~x;
+            if (y) begin
+                x = x * 3;
+                y = y + 1;
+            end
+        end
+    endtask
+    reg [7:0] a, b;
+    always @* t(a, b);
+    initial begin
+        a = 0;
+        b = 1;
+        $monitor("%d %b %b", $time, a, b);
+        repeat (100)
+            #5 b = b * 3 - 1;
+    end
+endmodule