sv2v/src/Language/SystemVerilog/AST/ModuleItem.hs

162 lines
5.0 KiB
Haskell
Raw Normal View History

{- sv2v
- Author: Zachary Snow <zach@zachjs.com>
- Initial Verilog AST Author: Tom Hawkins <tomahawkins@gmail.com>
-
- SystemVerilog `module` items
-}
module Language.SystemVerilog.AST.ModuleItem
( ModuleItem (..)
, PortBinding
, ParamBinding
, ModportDecl
, AlwaysKW (..)
, NInputGateKW (..)
, NOutputGateKW (..)
2020-03-21 02:13:57 +01:00
, AssignOption (..)
) where
import Data.List (intercalate)
import Text.Printf (printf)
import Language.SystemVerilog.AST.ShowHelp
import Language.SystemVerilog.AST.Attr (Attr)
2019-04-23 23:12:56 +02:00
import Language.SystemVerilog.AST.Decl (Direction)
import Language.SystemVerilog.AST.Description (PackageItem)
import Language.SystemVerilog.AST.Expr (Expr(Ident, Nil), Range, TypeOrExpr, showRanges)
import Language.SystemVerilog.AST.GenItem (GenItem)
import Language.SystemVerilog.AST.LHS (LHS)
2020-02-01 02:24:37 +01:00
import Language.SystemVerilog.AST.Stmt (Stmt, AssertionItem, Timing(Delay))
2020-03-21 02:13:57 +01:00
import Language.SystemVerilog.AST.Type (Identifier, DriveStrength)
data ModuleItem
= MIAttr Attr ModuleItem
| AlwaysC AlwaysKW Stmt
2020-03-21 02:13:57 +01:00
| Assign AssignOption LHS Expr
| Defparam LHS Expr
| Instance Identifier [ParamBinding] Identifier (Maybe Range) [PortBinding]
| Genvar Identifier
| Generate [GenItem]
| Modport Identifier [ModportDecl]
| Initial Stmt
2019-11-01 01:39:11 +01:00
| Final Stmt
| MIPackageItem PackageItem
2020-06-14 21:56:09 +02:00
| NInputGate NInputGateKW Expr Identifier LHS [Expr]
| NOutputGate NOutputGateKW Expr Identifier [LHS] Expr
| AssertionItem AssertionItem
deriving Eq
instance Show ModuleItem where
show (MIPackageItem i) = show i
show (MIAttr attr mi ) = printf "%s %s" (show attr) (show mi)
show (AlwaysC k b) = printf "%s %s" (show k) (show b)
2020-03-21 02:13:57 +01:00
show (Assign o a b) = printf "assign %s%s = %s;" (showPad o) (show a) (show b)
show (Defparam a b) = printf "defparam %s = %s;" (show a) (show b)
show (Genvar x ) = printf "genvar %s;" x
show (Generate b ) = printf "generate\n%s\nendgenerate" (indent $ unlines' $ map show b)
show (Modport x l) = printf "modport %s(\n%s\n);" x (indent $ intercalate ",\n" $ map showModportDecl l)
show (Initial s ) = printf "initial %s" (show s)
2019-11-01 01:39:11 +01:00
show (Final s ) = printf "final %s" (show s)
2020-02-01 02:24:37 +01:00
show (NInputGate kw d x lhs exprs) =
showGate kw d x $ show lhs : map show exprs
show (NOutputGate kw d x lhss expr) =
showGate kw d x $ (map show lhss) ++ [show expr]
2020-06-10 03:18:31 +02:00
show (AssertionItem (x, a)) =
if null x
then show a
2020-06-10 03:18:31 +02:00
else printf "%s : %s" x (show a)
show (Instance m params i r ports) =
if null params
then printf "%s %s%s%s;" m i rStr (showPorts ports)
else printf "%s #%s %s%s%s;" m (showParams params) i rStr (showPorts ports)
where rStr = maybe "" (\a -> showRanges [a] ++ " ") r
showPorts :: [PortBinding] -> String
showPorts ports = indentedParenList $ map showPort ports
showPort :: PortBinding -> String
2020-06-14 21:56:09 +02:00
showPort ("*", Nil) = ".*"
showPort (i, arg) =
if i == ""
2020-06-14 21:56:09 +02:00
then show arg
else printf ".%s(%s)" i (show arg)
2020-06-14 21:56:09 +02:00
showGate :: Show k => k -> Expr -> Identifier -> [String] -> String
2020-02-01 02:24:37 +01:00
showGate kw d x args =
printf "%s %s%s(%s);" (show kw) delayStr nameStr (commas args)
where
2020-06-14 21:56:09 +02:00
delayStr = if d == Nil then "" else showPad $ Delay d
2020-02-01 02:24:37 +01:00
nameStr = showPad $ Ident x
showParams :: [ParamBinding] -> String
showParams params = indentedParenList $ map showParam params
showParam :: ParamBinding -> String
showParam ("*", Right Nil) = ".*"
showParam (i, arg) =
printf fmt i (either show show arg)
where fmt = if i == "" then "%s%s" else ".%s(%s)"
showModportDecl :: ModportDecl -> String
2020-06-14 21:56:09 +02:00
showModportDecl (dir, ident, e) =
if e == Ident ident
then printf "%s %s" (show dir) ident
2020-06-14 21:56:09 +02:00
else printf "%s .%s(%s)" (show dir) ident (show e)
2020-06-14 21:56:09 +02:00
type PortBinding = (Identifier, Expr)
type ParamBinding = (Identifier, TypeOrExpr)
2020-06-14 21:56:09 +02:00
type ModportDecl = (Direction, Identifier, Expr)
data AlwaysKW
= Always
| AlwaysComb
| AlwaysFF
| AlwaysLatch
deriving Eq
instance Show AlwaysKW where
show Always = "always"
show AlwaysComb = "always_comb"
show AlwaysFF = "always_ff"
show AlwaysLatch = "always_latch"
data NInputGateKW
= GateAnd
| GateNand
| GateOr
| GateNor
| GateXor
| GateXnor
deriving Eq
instance Show NInputGateKW where
show GateAnd = "and"
show GateNand = "nand"
show GateOr = "or"
show GateNor = "nor"
show GateXor = "xor"
show GateXnor = "xnor"
data NOutputGateKW
= GateBuf
| GateNot
deriving Eq
instance Show NOutputGateKW where
show GateBuf = "buf"
show GateNot = "not"
2020-03-21 02:13:57 +01:00
data AssignOption
= AssignOptionNone
| AssignOptionDelay Expr
| AssignOptionDrive DriveStrength
deriving Eq
instance Show AssignOption where
show AssignOptionNone = ""
show (AssignOptionDelay de) = printf "#(%s)" (show de)
show (AssignOptionDrive ds) = show ds