mirror of https://github.com/zachjs/sv2v.git
16 lines
212 B
Systemverilog
16 lines
212 B
Systemverilog
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interface Interface;
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logic x;
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endinterface
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module Module(i, j);
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Interface i;
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logic j;
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assign i.x = j.x;
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endmodule
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module top;
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Interface i();
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Interface j();
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Module m(i, j);
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endmodule
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