mirror of https://github.com/zachjs/sv2v.git
12 lines
213 B
Verilog
12 lines
213 B
Verilog
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module child(
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input wire [8:0] inp,
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output reg [2:0] out
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);
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always @* begin
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case (inp[8:7])
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2'd0: out = inp[6:4];
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default: out = 3'd0;
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endcase
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end
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endmodule
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