mirror of https://github.com/zachjs/sv2v.git
11 lines
180 B
Verilog
11 lines
180 B
Verilog
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module top;
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reg [3:0] t;
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initial begin : blk
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reg [4:0] x;
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t = 1'sb1;
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x = t;
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$display("%b", t);
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$display("%b", x);
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end
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endmodule
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