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13 lines
228 B
Verilog
13 lines
228 B
Verilog
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module top;
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initial begin : block_name1
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integer i;
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i = 1;
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$display("%08d", i);
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end
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initial begin : block_name2
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integer i;
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i = 1;
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$display("%08d", i);
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end
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endmodule
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