test/basic/red_wrap.sv

module top;
    wire a, b, x, y;
    assign x = a | |b;
    assign y = a & &b;
endmodule
tweak codegen for bitwise binary followed by reduction unary 2024-01-04 22:09:04 -07:00			`module top;`
			`wire a, b, x, y;`
			`assign x = a \| \|b;`
			`assign y = a & &b;`
			`endmodule`