tweak codegen for bitwise binary followed by reduction unary

CHANGELOG.md

@@ -35,6 +35,7 @@
 * Added error checking for unresolved typenames
 * Added constant folding for `||` and `&&`
 * `input reg` module ports are now converted to `input wire`
+* `x | |y` and `x & &y` are now output as `x | (|y)` and `x & (&y)`
 
 ## v0.0.11
 

src/Language/SystemVerilog/AST/Expr.hs

@@ -121,7 +121,10 @@ instance Show Expr where
         shows o .
         showChar ' ' .
         showsAttrs a .
-        showBinOpPrec r
+        case (o, r) of
+            (BitAnd, UniOp RedAnd _) -> showExprWrapped r
+            (BitOr , UniOp RedOr  _) -> showExprWrapped r
+            _ -> showBinOpPrec r
     showsPrec _ (Dot      e n  ) =
         shows e .
         showChar '.' .
@@ -202,14 +205,17 @@ showRange :: Range -> String
 showRange (h, l) = '[' : show h ++ ':' : show l ++ "]"
 
 showUniOpPrec :: Expr -> ShowS
-showUniOpPrec e@UniOp{} = (showParen True . shows) e
-showUniOpPrec e@BinOp{} = (showParen True . shows) e
+showUniOpPrec e@UniOp{} = showExprWrapped e
+showUniOpPrec e@BinOp{} = showExprWrapped e
 showUniOpPrec e = shows e
 
 showBinOpPrec :: Expr -> ShowS
-showBinOpPrec e@BinOp{} = (showParen True . shows) e
+showBinOpPrec e@BinOp{} = showExprWrapped e
 showBinOpPrec e = shows e
 
+showExprWrapped :: Expr -> ShowS
+showExprWrapped = showParen True . shows
+
 type ParamBinding = (Identifier, TypeOrExpr)
 
 showParams :: [ParamBinding] -> String

test/basic/red_wrap.sv

@@ -0,0 +1,5 @@
+module top;
+    wire a, b, x, y;
+    assign x = a | |b;
+    assign y = a & &b;
+endmodule

test/basic/red_wrap.sv.pat

@@ -0,0 +1,4 @@
+affirm | (|
+affirm & (&
+reject | |
+reject & &