mirror of https://github.com/openXC7/prjxray.git
2.9 KiB
2.9 KiB
| 1 | #-------------------------------------------------------------------------------- |
|---|---|
| 2 | # Auto-generated by Migen (--------) & LiteX (3350d33f) on 2020-02-03 11:41:31 |
| 3 | #-------------------------------------------------------------------------------- |
| 4 | csr_base,ctrl,0x82000000,, |
| 5 | csr_base,identifier_mem,0x82001800,, |
| 6 | csr_base,timer0,0x82002000,, |
| 7 | csr_base,ddrphy,0x82002800,, |
| 8 | csr_base,sdram,0x82004000,, |
| 9 | csr_register,ctrl_reset,0x82000000,1,rw |
| 10 | csr_register,ctrl_scratch,0x82000004,4,rw |
| 11 | csr_register,ctrl_bus_errors,0x82000014,4,ro |
| 12 | csr_register,timer0_load,0x82002000,4,rw |
| 13 | csr_register,timer0_reload,0x82002010,4,rw |
| 14 | csr_register,timer0_en,0x82002020,1,rw |
| 15 | csr_register,timer0_update_value,0x82002024,1,rw |
| 16 | csr_register,timer0_value,0x82002028,4,ro |
| 17 | csr_register,timer0_ev_status,0x82002038,1,rw |
| 18 | csr_register,timer0_ev_pending,0x8200203c,1,rw |
| 19 | csr_register,timer0_ev_enable,0x82002040,1,rw |
| 20 | csr_register,ddrphy_half_sys8x_taps,0x82002800,1,rw |
| 21 | csr_register,ddrphy_cdly_rst,0x82002804,1,rw |
| 22 | csr_register,ddrphy_cdly_inc,0x82002808,1,rw |
| 23 | csr_register,ddrphy_dly_sel,0x8200280c,1,rw |
| 24 | csr_register,ddrphy_rdly_dq_rst,0x82002810,1,rw |
| 25 | csr_register,ddrphy_rdly_dq_inc,0x82002814,1,rw |
| 26 | csr_register,ddrphy_rdly_dq_bitslip_rst,0x82002818,1,rw |
| 27 | csr_register,ddrphy_rdly_dq_bitslip,0x8200281c,1,rw |
| 28 | csr_register,sdram_dfii_control,0x82004000,1,rw |
| 29 | csr_register,sdram_dfii_pi0_command,0x82004004,1,rw |
| 30 | csr_register,sdram_dfii_pi0_command_issue,0x82004008,1,rw |
| 31 | csr_register,sdram_dfii_pi0_address,0x8200400c,2,rw |
| 32 | csr_register,sdram_dfii_pi0_baddress,0x82004014,1,rw |
| 33 | csr_register,sdram_dfii_pi0_wrdata,0x82004018,4,rw |
| 34 | csr_register,sdram_dfii_pi0_rddata,0x82004028,4,ro |
| 35 | csr_register,sdram_dfii_pi1_command,0x82004038,1,rw |
| 36 | csr_register,sdram_dfii_pi1_command_issue,0x8200403c,1,rw |
| 37 | csr_register,sdram_dfii_pi1_address,0x82004040,2,rw |
| 38 | csr_register,sdram_dfii_pi1_baddress,0x82004048,1,rw |
| 39 | csr_register,sdram_dfii_pi1_wrdata,0x8200404c,4,rw |
| 40 | csr_register,sdram_dfii_pi1_rddata,0x8200405c,4,ro |
| 41 | csr_register,sdram_dfii_pi2_command,0x8200406c,1,rw |
| 42 | csr_register,sdram_dfii_pi2_command_issue,0x82004070,1,rw |
| 43 | csr_register,sdram_dfii_pi2_address,0x82004074,2,rw |
| 44 | csr_register,sdram_dfii_pi2_baddress,0x8200407c,1,rw |
| 45 | csr_register,sdram_dfii_pi2_wrdata,0x82004080,4,rw |
| 46 | csr_register,sdram_dfii_pi2_rddata,0x82004090,4,ro |
| 47 | csr_register,sdram_dfii_pi3_command,0x820040a0,1,rw |
| 48 | csr_register,sdram_dfii_pi3_command_issue,0x820040a4,1,rw |
| 49 | csr_register,sdram_dfii_pi3_address,0x820040a8,2,rw |
| 50 | csr_register,sdram_dfii_pi3_baddress,0x820040b0,1,rw |
| 51 | csr_register,sdram_dfii_pi3_wrdata,0x820040b4,4,rw |
| 52 | csr_register,sdram_dfii_pi3_rddata,0x820040c4,4,ro |
| 53 | constant,config_clock_frequency,50000000,, |
| 54 | constant,config_cpu_type,none,, |
| 55 | constant,config_cpu_type_none,None,, |
| 56 | constant,config_csr_alignment,32,, |
| 57 | constant,config_csr_data_width,8,, |
| 58 | constant,config_l2_size,32,, |
| 59 | constant,config_shadow_base,2147483648,, |
| 60 | memory_region,sram,0x01000000,4096,cached |
| 61 | memory_region,csr,0x82000000,65536,cached |
| 62 | memory_region,main_ram,0x40000000,268435456,cached |