mirror of https://github.com/openXC7/prjxray.git
46 lines
2.1 KiB
Markdown
46 lines
2.1 KiB
Markdown
# BEL timings fuzzer
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This fuzzer is suppose to extract all the BEL timings for Xilinx 7-series FPGAs.
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The extracted timings are saved as SDF files.
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Single SDF file is produced for every FPGA tile type.
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## Fuzzer flow
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Fuzzer flow is the following:
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Vivado/`runme.tcl` -> `fixup_timings_txt.py` -> `tim2json.py` -> `makesdf.py` -> `sdfmerge.py`
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The fuzzer uses Vivado tcl script to read all the FPGA timings data.
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This data is dumped to a text file.
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Beside timings data the tcl scipt dumps the following information:
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* Sites pins
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* BELs pins
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* BELs attributes
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The tcl script iterates over every BEL for all the sites in each tile type.
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The timings, pins and attributes are dumped in the same hierarchy.
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This hierarchy is used by the `tim2json` script to process the txt dump.
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Main task of the `tim2json` script is to figure out what the dumped timings mean and what paths do they describe.
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This is done by parsing the string timings, searching the BEL/Sites pins and BEL attributes.
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Since for some pins there was no naming convention, the names are provided directly via `pin_alias_map.json`.
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Some BELs (e.g. BRAMs) reports the timings with incorrect site name.
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To work around this issue the `fixup_timings_txt.py` script is used to flatten the timings dump file.
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As a result all the timings for a selected tile are squashed into one site.
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### Text files format
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The files dumped by the Vivado scrips have the following format:
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Each line starts with a tile name, proceeded by a number of sites in the tile.
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After the tiles count, each tile info is placed.
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The tile info starts with a tile name followed by number of BELs in the tile.
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The bels number is followed by BEL entries.
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Each BEL entry starts with BEL name followed by a number of entries.
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The entries differ between the file types:
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* timings file: each timing entry starts with entry name followed by 5 timings values
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* properties file: each properties entry starts with property name followed by a number of possible property values, followed by a list of the possible property values
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* pins file: each pin entry starts with pin name, followed by pin direction (IN/OUT), followed by 0 or 1 flag saying if the pin is a clock pin
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