mirror of https://github.com/openXC7/prjxray.git
154 lines
3.8 KiB
Python
154 lines
3.8 KiB
Python
'''
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Generate a primitive to place at every I/O
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Unlike CLB tests, the LFSR for this is inside the ROI, not driving it
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'''
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import os
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import random
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray.db import Database
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from prjxray import verilog
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def gen_iobs():
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'''
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IOB33S: main IOB of a diff pair
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IOB33M: secondary IOB of a diff pair
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IOB33: not a diff pair. Relatively rare (at least in ROI...2 of them?)
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Focus on IOB33S to start
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'''
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db = Database(util.get_db_root())
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grid = db.grid()
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for tile_name in grid.tiles():
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loc = grid.loc_of_tilename(tile_name)
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gridinfo = grid.gridinfo_at_loc(loc)
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for site_name, site_type in gridinfo.sites.items():
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if site_type in ['IOB33S']:
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yield site_name, site_type
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def write_params(ports):
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pinstr = ''
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for site, (name, dir_, cell) in sorted(ports.items(), key=lambda x: x[1]):
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# pinstr += 'set_property -dict "PACKAGE_PIN %s IOSTANDARD LVCMOS33" [get_ports %s]' % (packpin, port)
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pinstr += '%s,%s,%s,%s\n' % (site, name, dir_, cell)
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open('params.csv', 'w').write(pinstr)
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def run():
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# All possible values
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iosites = {}
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for site_name, site_type in gen_iobs():
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iosites[site_name] = site_type
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# Assigned in this design
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ports = {}
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DIN_N = 0
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DOUT_N = 0
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def remain_sites():
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return set(iosites.keys()) - set(ports.keys())
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def rand_site():
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'''Get a random, unused site'''
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return random.choice(list(remain_sites()))
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def assign_i(site, name):
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nonlocal DIN_N
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assert site not in ports
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cell = "di_bufs[%u].ibuf" % DIN_N
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DIN_N += 1
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ports[site] = (name, 'input', cell)
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def assign_o(site, name):
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nonlocal DOUT_N
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assert site not in ports
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cell = "do_bufs[%u].obuf" % DOUT_N
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DOUT_N += 1
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ports[site] = (name, 'output', cell)
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# Assign at least one di and one do
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assign_i(rand_site(), 'di[0]')
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assign_o(rand_site(), 'do[0]')
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# Now assign the rest randomly
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while len(remain_sites()):
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if random.randint(0, 1):
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assign_i(rand_site(), 'di[%u]' % DIN_N)
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else:
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assign_o(rand_site(), 'do[%u]' % DOUT_N)
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write_params(ports)
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print(
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'''
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`define N_DI %u
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`define N_DO %u
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module top(input wire [`N_DI-1:0] di, output wire [`N_DO-1:0] do);
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genvar i;
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//Instantiate BUFs so we can LOC them
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wire [`N_DI-1:0] di_buf;
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generate
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for (i = 0; i < `N_DI; i = i+1) begin:di_bufs
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IBUF ibuf(.I(di[i]), .O(di_buf[i]));
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end
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endgenerate
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wire [`N_DO-1:0] do_unbuf;
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generate
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for (i = 0; i < `N_DO; i = i+1) begin:do_bufs
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OBUF obuf(.I(do_unbuf[i]), .O(do[i]));
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end
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endgenerate
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roi roi(.di(di_buf), .do(do_unbuf));
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endmodule
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//Arbitrary terminate into LUTs
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module roi(input wire [`N_DI-1:0] di, output wire [`N_DO-1:0] do);
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genvar i;
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generate
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for (i = 0; i < `N_DI; i = i+1) begin:dis
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(* KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'h8000_0000_0000_0001)
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) lut (
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.I0(di[i]),
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.I1(di[i]),
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.I2(di[i]),
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.I3(di[i]),
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.I4(di[i]),
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.I5(di[i]),
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.O());
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end
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endgenerate
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generate
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for (i = 0; i < `N_DO; i = i+1) begin:dos
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(* KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'h8000_0000_0000_0001)
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) lut (
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.I0(),
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.I1(),
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.I2(),
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.I3(),
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.I4(),
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.I5(),
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.O(do[i]));
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end
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endgenerate
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endmodule
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''' % (DIN_N, DOUT_N))
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if __name__ == '__main__':
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run()
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