mirror of https://github.com/openXC7/prjxray.git
22 lines
570 B
Tcl
22 lines
570 B
Tcl
source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property IS_ENABLED 0 [get_drc_checks {DSPS-3}]
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set_property IS_ENABLED 0 [get_drc_checks {DSPS-5}]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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}
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run
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