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https://github.com/openXC7/prjxray.git
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Dr Jonathan Richard Robert KimmittandClaude Opus 4.7
39f5de415d
Port prjxray to the Virtex-7 family, modelled on Kintex-7, targeting xc7vx485tffg1761-2 (vc707). Non-breaking for the existing families. Family registration: - settings/virtex7.sh, settings/virtex7/devices.yaml - Makefile: virtex7 in DATABASES/XRAY_PARTS + db-extras-virtex7 targets - utils/update_parts.py, update_resources.py: virtex7 choice - CI matrix (Pipeline.yml), Vivado edition (xilinx.sh), README Architecture adaptations for the HP-bank-only VX part (verified non-breaking): - update_resources.tcl: fall back to HP banks when no HR banks exist - XRAY_IOSTANDARD env (default LVCMOS33; LVCMOS18 for virtex7), parameterised across the fuzzer generate.tcl files - fuzzers: enable HP-bank (iob18/ioi18) + IOI/HCLK handling for virtex7; GTX skipped (ffg1761 bonds only ~7 of 14 GTX quads) - 005-tilegrid: HP/HR bank tile handling; iob18_int INT offset 3->2; ioi18 AUTO_FRAME; cfg PDRC-2 DRC disable; add_tdb skips unsolved edge tiles; per-specimen retry for transient FlexLM SIGSEGV under concurrency - per-family Vivado version gate (virtex7 -> v2020.1.1) - XRAY_ROI and XRAY_ROI_GRID tuned to a compact CLBLL+CLBLM region General fixes: - tools/bitread.cc: fix use-after-free of the mmap'd bitstream (exposed by the larger Virtex-7 bitstream) - utils/environment.python.sh: add repo root to PYTHONPATH (PEP 660 editable install doesn't expose the repo-root utils/ package) Co-Authored-By: Claude Opus 4.7 <[email protected]>
34 lines
1.1 KiB
Tcl
34 lines
1.1 KiB
Tcl
# Copyright (C) 2017-2021 The Project X-Ray Authors
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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# Writes a JSON5 to filename containing timing for current design.
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# This can be used with create_timing_worksheet_db.py to compare prjxray model
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# with Vivado timing model outputs.
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link_design -part $::env(XRAY_PART)
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# one pin -> 0
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set clk_pins [get_package_pins -filter "IS_CLK_CAPABLE"]
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# three pins -> 1, 2, 3 on HR banks. High-performance-bank-only parts (e.g.
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# Virtex-7 "VX" devices) have no high-range banks, so fall back to HP banks.
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set banks [get_iobanks -filter "BANK_TYPE==BT_HIGH_RANGE"]
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if {$banks == ""} {
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set banks [get_iobanks -filter "BANK_TYPE==BT_HIGH_PERFORMANCE"]
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}
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set data_pins ""
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foreach bank [split $banks " "] {
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append data_pins " " [get_package_pins -filter "IS_GENERAL_PURPOSE && BANK==$bank"]
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}
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set fp [open $::env(TMP_FILE) w]
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puts $fp "{"
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puts $fp "\t\"clk_pins\": \"$clk_pins\","
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puts $fp "\t\"data_pins\": \"$data_pins\""
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puts $fp "}"
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