luke
/
prjxray
mirror of https://github.com/openXC7/prjxray.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
prjxray/fuzzers/011-clb-ffconfig
History
Keith Rothman 01a0be3162 Add support to zero db to support simple groups. 
Previously these kinds of zero groups would require encoding the
final bits, rather than tags.  This is extends the dbfixup to
construct groups via groups of tags, rather than groups of bits.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 		2019-06-19 14:46:39 -07:00
..
minitest minitest: clean up folders 2019-01-07 23:31:44 +01:00
Makefile Add support to zero db to support simple groups. 2019-06-19 14:46:39 -07:00
README.md clb: clean up README files 2019-01-11 18:52:42 +01:00
bits.dbf Add support to zero db to support simple groups. 2019-06-19 14:46:39 -07:00
generate.py Add support to zero db to support simple groups. 2019-06-19 14:46:39 -07:00
generate.sh fuzzers: name with tile type 2019-01-07 23:08:45 +01:00
generate.tcl fuzzers: name with tile type 2019-01-07 23:08:45 +01:00
prims.py fuzzers: name with tile type 2019-01-07 23:08:45 +01:00
top.py 01x-clb/top.py: Added CLBN increment from env var 2019-01-17 15:31:50 +01:00

README.md

clb-ffconfig Fuzzer

Documents FF configuration.

Note Vivado GUI is misleading in some cases where it shows configuration per FF, but its actually per SLICE

Primitive pin map

Element CE CK D SR Q
FDRE CE C D R Q
FDPE CE C D PRE Q
FDSE CE C D S Q
FDCE CE C D CLR Q
LDPE GE G D PRE Q
LDCE GE G D CLR Q

Primitive bit map

Prim FFSYNC LATCH ZRST
FDPE
FDSE X
FDRE X X
FDCE X
LDCE X X
LDPE X

FFSYNC

Configures whether a storage element is synchronous or asynchronous.

Scope: entire site (not individual FFs)

FFSYNC Reset Applicable prims
0 Synchronous FDPE, FDCE, LDCE, LDPE
1 Asynchronous FDSE, FDRE

LATCH

Configures latch vs FF behavior for the CLB

LATCH Description Primitives
0 All storage elements in the CLB are FF's FDPE, FDSE, FDRE, FDCE
1 LUT6 storage elements are latches (LDCE or LDPE). LUT5 storage elements cannot be used LDCE, LDPE

N*FF.ZRST

Configures stored value when reset is asserted

Prim ZRST On reset
FDRE, FDCE, and LDCE 0 1
FDRE, FDCE, and LDCE 1 0
FDPE, FDSE, and LDPE 0 0
FDPE, FDSE, and LDPE 1 1

N*FF.ZINI

Sets GSR FF or latch value

LATCH ZINI Set to
FF 0 1
FF 1 0
LATCH 0 0
LATCH 1 1

CEUSEDMUX

Configures ability to drive clock enable (CE) or always enable clock

CEUSEDMUX Description
0 always on (CE=1)
1 controlled (CE=mywire)

SRUSEDMUX

Configures ability to reset FF after GSR

SRUSEDMUX Description
0 never reset (R=0)
1 controlled (R=mywire)

TODO: how used when SR?

CLKINV

Configures whether to invert the clock going into a slice.

Scope: entire site (not individual FFs)

LATCH CLKINV Description
FF 0 normal clock
FF 1 invert clock
LATCH 0 invert clock
LATCH 1 normal clock