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Dr Jonathan Richard Robert KimmittandClaude Opus 4.7
3119e42d25
- settings/virtex7.sh: move XRAY_ROI and XRAY_ROI_GRID off the device bottom edge (SLICE_X0Y50:X11Y99; grid 5-20/261-312). Edge tiles at Y0 can't exercise features like BRAM36 ECC/cascade, and the bottom-edge BRAM is unsolvable. - prjxray/segmaker.py: when a tile has no bitstream info (dummy tile, or an edge tile dropped from the tilegrid such as BRAM_L_X114Y0 on xc7vx485t), account for any tags on it and skip with a warning instead of asserting. Fixes the BRAM config/FIFO fuzzers (027, 029, ...) for virtex7; no-op for normal dummy tiles. Also print the unsolved tags before the all-tags-used assertion. - fuzzers/Makefile: skip 018-clb-ram for virtex7 (Vivado 2020.1 packs SRL/RAM into different BEL slots than the fuzzer pins). Co-Authored-By: Claude Opus 4.7 <[email protected]>