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Tim 'mithro' Ansell 75e9a2acd9 Fix the output of internal routing MUXs in the CLBs. 
Before;
```
CLBLL_L.SLICEL_X1.A5FFMUX
Bit Name                        Position
CLBLL_L.SLICEL_X1.A5FFMUX.IN_A  31_08
CLBLL_L.SLICEL_X1.A5FFMUX.IN_B  31_11
```

After;
```
PIPs driving CLBLL_L.SLICEL_X0.B5FFMUX
PIP                            30_18  30_19
CLBLL_L.SLICEL_X0.B5FFMUX.IN_B   1      -
CLBLL_L.SLICEL_X0.B5FFMUX.IN_A   -      1
```

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 		2019-02-26 19:32:24 -08:00
..
.gitignore Some refactoring 2017-12-20 22:46:39 +01:00
htmlgen.py Fix the output of internal routing MUXs in the CLBs. 2019-02-26 19:32:24 -08:00