luke
/
prjxray
mirror of https://github.com/openXC7/prjxray.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix the output of internal routing MUXs in the CLBs. 

Before;
```
CLBLL_L.SLICEL_X1.A5FFMUX
Bit Name                        Position
CLBLL_L.SLICEL_X1.A5FFMUX.IN_A  31_08
CLBLL_L.SLICEL_X1.A5FFMUX.IN_B  31_11
```

After;
```
PIPs driving CLBLL_L.SLICEL_X0.B5FFMUX
PIP                            30_18  30_19
CLBLL_L.SLICEL_X0.B5FFMUX.IN_B   1      -
CLBLL_L.SLICEL_X0.B5FFMUX.IN_A   -      1
```

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
This commit is contained in:
Tim 'mithro' Ansell 2019-02-26 19:32:24 -08:00
parent 01a1289bcf
commit 75e9a2acd9
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
htmlgen/htmlgen.py
View File

@ -110,7 +110,7 @@ def db_read(dbstate, tiletype, db_dir):
add_pip_bits(tag, bits)
elif tiletype in ["clbll_l", "clbll_r", "clblm_l", "clblm_r"] and \
re.search(r"(\.[ABCD]MUX\.)|(\.PRECYINIT\.)", tag):
re.search(r"(\.[ABCD].*MUX\.)|(\.PRECYINIT\.)", tag):
add_pip_bits(tag, bits)
else: