mirror of https://github.com/openXC7/prjxray.git
54 lines
2.0 KiB
Markdown
54 lines
2.0 KiB
Markdown
# FASM Proof of Concept using Vivado Partial Reconfig flow
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top.v is a top-level design that routes a variety of signal into a black-box
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region of interest (ROI). Vivado's Partial Reconfiguration flow (see UG909
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and UG947) is used to implement that design and obtain a bitstream that
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configures portions of the chip that are currently undocumented.
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Designs that fit within the ROI are written in FASM and merged with the above
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harness into a bitstream with fasm2frame and xc7patch.
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# Usage
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make rules are provided for generating each step of the process so that
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intermediate forms can be analyzed. Assuming you have a .fasm file, invoking
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the %.hand\_crafted.bit rule will generate a merged bitstream:
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```
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make foo.hand\_crafted.bit # reads foo.fasm
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```
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# Using Vivado to generate .fasm
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Vivado's Partial Reconfiguration flow can be used to synthesize and implement a
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design that is then converted to .fasm. The basic process is to write a module
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that _exactly_ matches the roi blackbox in the top-level design. Note that
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even the name of the module must match exactly. Once you have a design, the
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first step is to synthesize the design with -mode out\_of\_context:
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```
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read_verilog <design>.v
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synth_design -mode out_of_context -top roi -part $::env(XRAY_PART)
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write_checkpoint -force <design>.dcp
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```
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Next, implement that design within the harness. Run 'make harness\_routed.dcp'
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if it doesn't already exist. The following TCL will load the fully-routed
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harness, load your synthesized design, and generate a bitstream containing
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both:
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```
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open_checkpoint -force harness_routed.dcp
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read_checkpoint -cell <design>.dcp
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opt_design
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place_design
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route_design
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write_checkpoint -force <design>_routed.dcp
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write_bitstream -force <design>_routed.bit
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```
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'make <design>\_routed.fasm' will run a sequence of tools to extract the bits
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that are inside the ROI and convert them to FASM. The resulting .fasm can be
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used to generate a marged bitstream using
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'make <design>\_routed.hand\_crafted.bit'. The resulting bitstream should be
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equivalent to <design>\_routed.bit.
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