luke
/
prjxray
mirror of https://github.com/openXC7/prjxray.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
prjxray/fuzzers/030-iob/minitest
History
Dr Jonathan Richard Robert Kimmitt 39f5de415d Add Virtex-7 (xc7vx485t) family support 
Port prjxray to the Virtex-7 family, modelled on Kintex-7, targeting
xc7vx485tffg1761-2 (vc707). Non-breaking for the existing families.

Family registration:
- settings/virtex7.sh, settings/virtex7/devices.yaml
- Makefile: virtex7 in DATABASES/XRAY_PARTS + db-extras-virtex7 targets
- utils/update_parts.py, update_resources.py: virtex7 choice
- CI matrix (Pipeline.yml), Vivado edition (xilinx.sh), README

Architecture adaptations for the HP-bank-only VX part (verified non-breaking):
- update_resources.tcl: fall back to HP banks when no HR banks exist
- XRAY_IOSTANDARD env (default LVCMOS33; LVCMOS18 for virtex7), parameterised
  across the fuzzer generate.tcl files
- fuzzers: enable HP-bank (iob18/ioi18) + IOI/HCLK handling for virtex7;
  GTX skipped (ffg1761 bonds only ~7 of 14 GTX quads)
- 005-tilegrid: HP/HR bank tile handling; iob18_int INT offset 3->2;
  ioi18 AUTO_FRAME; cfg PDRC-2 DRC disable; add_tdb skips unsolved edge tiles;
  per-specimen retry for transient FlexLM SIGSEGV under concurrency
- per-family Vivado version gate (virtex7 -> v2020.1.1)
- XRAY_ROI and XRAY_ROI_GRID tuned to a compact CLBLL+CLBLM region

General fixes:
- tools/bitread.cc: fix use-after-free of the mmap'd bitstream (exposed by the
  larger Virtex-7 bitstream)
- utils/environment.python.sh: add repo root to PYTHONPATH (PEP 660 editable
  install doesn't expose the repo-root utils/ package)

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
 		2026-05-24 07:21:23 +01:00
..
DRIVE.tcl Add license headers to tcl files 2020-05-26 07:33:12 -07:00
IOSTANDARD.tcl Add license headers to tcl files 2020-05-26 07:33:12 -07:00
Makefile Add licensing header to Makefiles 2020-05-26 07:33:12 -07:00
PULLTYPE.tcl Add license headers to tcl files 2020-05-26 07:33:12 -07:00
README.md MAKE - Format Trailing Whitespace 2019-10-26 10:04:52 +01:00
SLEW.tcl Add license headers to tcl files 2020-05-26 07:33:12 -07:00
compare.py Add licensing header to fuzzers' python scripts 2020-05-26 07:33:12 -07:00
diff.mk iob: move minitest to fuzzer 2018-12-10 17:30:06 -08:00
diff_tcl.mk iob: move minitest to fuzzer 2018-12-10 17:30:06 -08:00
generate.tcl Add license headers to tcl files 2020-05-26 07:33:12 -07:00
params.csv minitest: Add csv generation script 2019-02-18 08:14:21 +01:00
runme.sh Add licensing header to bash scripts 2020-05-26 07:33:12 -07:00
runme.tcl Add Virtex-7 (xc7vx485t) family support 2026-05-24 07:21:23 +01:00
runme_tcl.sh Add licensing header to bash scripts 2020-05-26 07:33:12 -07:00
sweep.tcl Add license headers to tcl files 2020-05-26 07:33:12 -07:00
tcl.v iob: move minitest to fuzzer 2018-12-10 17:30:06 -08:00
template.tcl Add Virtex-7 (xc7vx485t) family support 2026-05-24 07:21:23 +01:00
top.py Add or fix license header 2020-05-26 07:33:12 -07:00
top.v MAKE - Format Trailing Whitespace 2019-10-26 10:04:52 +01:00

README.md

PULLTYPE

PULLTYPE 38_98 39_97 39_97 NONE X KEEPER X X PULLDOWN PULLUP X X

DRIVE

Drive strength depends on current IOSTANDARD, e.g.

LVCMOS18 DRIVE 38_64 38_66 38_72 38_74 39_65 39_73 4 X X X 8 X X X 12 X X X 16 X X X 24 X X X

LVCMOS25 DRIVE 38_64 38_66 38_72 38_74 39_65 39_73 4 X X X 8 X 12 16 X X X

LVCMOS33 DRIVE 38_64 38_66 38_72 38_74 39_65 39_73 4 X X X 8 X X X 12 X X X 16 X X X

The minitest contains a csv target which generates a csv with differences across all LVCMOS and LVTTL standards for all supported DRIVE strengths and both slew rates.

IOSTANDARD

Effects bits, TBD exactly how Sample output:

diff LVCMOS33.bits LVTTL.bits < bit_00020026_006_00

bit_00020026_006_08

diff LVCMOS33.bits PCI33_3.bits < bit_00020026_006_02 < bit_00020026_006_18 < bit_00020026_006_22

bit_00020026_006_10 bit_00020026_006_16 bit_00020026_006_20 bit_00020027_006_11 bit_00020027_006_15