History

Dr Jonathan Richard Robert Kimmitt 39f5de415d Add Virtex-7 (xc7vx485t) family support Port prjxray to the Virtex-7 family, modelled on Kintex-7, targeting xc7vx485tffg1761-2 (vc707). Non-breaking for the existing families. Family registration: - settings/virtex7.sh, settings/virtex7/devices.yaml - Makefile: virtex7 in DATABASES/XRAY_PARTS + db-extras-virtex7 targets - utils/update_parts.py, update_resources.py: virtex7 choice - CI matrix (Pipeline.yml), Vivado edition (xilinx.sh), README Architecture adaptations for the HP-bank-only VX part (verified non-breaking): - update_resources.tcl: fall back to HP banks when no HR banks exist - XRAY_IOSTANDARD env (default LVCMOS33; LVCMOS18 for virtex7), parameterised across the fuzzer generate.tcl files - fuzzers: enable HP-bank (iob18/ioi18) + IOI/HCLK handling for virtex7; GTX skipped (ffg1761 bonds only ~7 of 14 GTX quads) - 005-tilegrid: HP/HR bank tile handling; iob18_int INT offset 3->2; ioi18 AUTO_FRAME; cfg PDRC-2 DRC disable; add_tdb skips unsolved edge tiles; per-specimen retry for transient FlexLM SIGSEGV under concurrency - per-family Vivado version gate (virtex7 -> v2020.1.1) - XRAY_ROI and XRAY_ROI_GRID tuned to a compact CLBLL+CLBLM region General fixes: - tools/bitread.cc: fix use-after-free of the mmap'd bitstream (exposed by the larger Virtex-7 bitstream) - utils/environment.python.sh: add repo root to PYTHONPATH (PEP 660 editable install doesn't expose the repo-root utils/ package) Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>		2026-05-24 07:21:23 +01:00
..
minitest	Add licensing header to Makefiles	2020-05-26 07:33:12 -07:00
Makefile	Add some determinism to the randomness in 018.	2020-09-11 10:51:21 -07:00
README.md	docs: Fix top level headers and other small clean.	2019-04-03 19:26:28 -07:00
generate.py	Add licensing header to fuzzers' python scripts	2020-05-26 07:33:12 -07:00
generate.sh	Add licensing header to bash scripts	2020-05-26 07:33:12 -07:00
generate.tcl	Add Virtex-7 (xc7vx485t) family support	2026-05-24 07:21:23 +01:00
top.py	Make 018 more robust by selectively disabling inputs and outputs.	2020-09-25 12:59:57 -07:00

README.md

clb-ram Fuzzer

Primitive	RAM	SMALL	SRL
LUT6
SRL16E		X	X
SRLC32E			X
RAM32X1S	X	X
RAM64X1S	X
RAM32M	X	X
RAM32X1D	X	X
RAM64M	X
RAM64X1D	X
RAM128X1D	X
RAM256X1S	X
RAM128X1S	X

NLUT.RAM

Set to make a RAM* family primitive, otherwise is a SRL or LUT function generator.

NLUT.SMALL

Seems to be set on smaller primitives.

NLUT.SRL

Whether to make a shift register LUT (SRL). Set when using SRL16E or SRLC32E

WA7USED

Set to 1 to propagate CLB's CX input to WA7

WA8USED

Set to 1 to propagate CLB's BX input to WA8

WEMUX.CE

WEMUX.CE	CLB RAM write enable
0	CLB WE input
1	CLB CE input