litghost f02800daf5 Merge pull request #1218 from antmicro/ddr-uart-bridge ...

Added UART DDR minitest

2020-02-26 17:13:38 -08:00

..

clb-bused

MAKE - Format Trailing Whitespace

2019-10-26 10:04:52 +01:00

clb-carry_cin_cyinit

minitest: clean up folders

2019-01-07 23:31:44 +01:00

clb-configs

minitest: clean up folders

2019-01-07 23:31:44 +01:00

clb-muxf8

MAKE - Format Trailing Whitespace

2019-10-26 10:04:52 +01:00

clkbuf

introduce vivado wrapper

2018-12-28 19:05:49 +01:00

eccbits

introduce vivado wrapper

2018-12-28 19:05:49 +01:00

fixedpnr

MAKE - Format Trailing Whitespace

2019-10-26 10:04:52 +01:00

iostandard

Added ignoring of PUDC_B pin.

2019-12-09 14:40:35 +01:00

iserdes.idelay

MAKE - Format Trailing Whitespace

2019-10-26 10:04:52 +01:00

iserdes.sdr_ddr

MAKE - Format Trailing Whitespace

2019-10-26 10:04:52 +01:00

litex

Merge pull request #1218 from antmicro/ddr-uart-bridge

2020-02-26 17:13:38 -08:00

litex_litedram

minitests/litex*: Fix location of clean_json5.py tool.

2020-02-24 23:07:48 -08:00

lvb_long_mux

introduce vivado wrapper

2018-12-28 19:05:49 +01:00

nodes_wires_list

tcl: reformat existing code

2018-12-05 16:52:56 -08:00

oserdes

MAKE - Format Trailing Whitespace

2019-10-26 10:04:52 +01:00

partial_reconfig_flow

MAKE - Format Trailing Whitespace

2019-10-26 10:04:52 +01:00

picorv32-v

introduce vivado wrapper

2018-12-28 19:05:49 +01:00

picorv32-y

introduce vivado wrapper

2018-12-28 19:05:49 +01:00

pip-switchboxes

minitest: clean up folders

2019-01-07 23:31:44 +01:00

plle2_adv

Merge pull request #1122 from JakeMercer/whitespace

2019-10-29 15:04:39 -07:00

roi_harness

Fix up Makefile dependences.

2020-02-19 16:34:12 -08:00

srl

Added generation of sorted and "uniqued" FASM output

2019-07-05 12:03:30 +02:00

tiles_wires_pips

introduce vivado wrapper

2018-12-28 19:05:49 +01:00

timing

Fix some bugs present timing analysis script.

2020-02-13 13:19:46 -08:00

util

introduce vivado wrapper

2018-12-28 19:05:49 +01:00

z7_blinky_emio

A minitest for Zynq7 EMIO PS->PL interface.

2019-12-03 15:39:13 +01:00